1. Field of the Invention
This invention relates to a method for fabricating gate electrodes of semiconductor integrated circuits, and more particularly, to a method of forming gate electrodes of low sheet resistance for embedded dynamic random access memory (DRAM) devices.
2. Description of the Prior Art
Advances in the semiconductor process technologies have significantly reduced the device feature size and increased the circuit density and performance on semiconductor chips. Incorporation of both logic and memory circuitry on a semiconductor chip has become a critical issue in the semiconductor industry. For example, Sung in U.S. Pat. No. 5,858,831 discloses a process for fabricating such logic and embedded DRAM device on a single semiconductor chip.
A metal oxide semiconductor (MOS) transistor element uses a gate electrode to control the output voltage thereof. Metals of low resistivity have been widely applied to form the gate electrode of a MOS field effect transistor (FET) that is used extensively for Ultra Large Scale Integration (ULSI). When the length of gate electrode is more than 2 xcexcm, aluminum is the very popular material for making the gate electrode of FET throughout the industry. As the semiconductor technology evolves into the sub-micron era, polysilicon replaces the conventional low resistance metals for making the gate electrode of FET with suitable threshold voltage. Recently, polycide structure composed of polysilicon and a transition metal silicide and salicide (self-aligned silicide) process are commonly used to reduce the sheet resistance of the gate electrode, as disclosed in Abemathey et al, U.S. Pat. No. 4,755,478, and Lang et al, U.S. Pat. No. 5,665,623.
In practice, the evolvement of semiconductor technologies has reduced the sheet resistance of the gate electrode from highly doped polysilicon of 45 xcexa9/square to tungsten silicide of 20 xcexa9/square and further to salicide of 10 xcexa9/square. However, the sheet resistance of the gate electrode is increased as electrical elements shrink. Therefore, there are currently a number of research projects for exploring a gate electrode of lower resistivity than 10 xcexa9/square to meet the development of high performance logic circuitry.
Accordingly, an object of the present invention is to provide a method for making gate electrodes of the FETs for embedded DRAM devices.
Another object of the present invention is to provide a method for making gate electrodes of low sheet resistance for embedded DRAM devices.
According to the present invention, a method of manufacturing a semiconductor device having a gate electrode of low sheet resistance comprising the steps of: defining active areas of MOS devices on a semiconductor substrate of one conductivity type and isolation regions spaced apart in the substrate; forming a first insulating film on the active areas; forming an electrode material on the first insulating film; forming a second insulating film used as a cap portion on the electrode material; patterning by the lithography technology and etching the second insulating film and the electrode material leaving portions over the active areas; forming lightly doped source/drain regions in the active areas by ion implantation; forming spacers on sidewalls of the electrode material and the second insulating film; forming source/drain diffusion regions; depositing an interlayer dielectric on the semiconductor substrate and etching back the dielectric layer to expose the second insulating layer; removing the second insulating film on the electrode material; and depositing a metal and removing the metal on the interlayer dielectric while leaving the metal on the electrode material.